Broadcom announced sampling of its 5nm ASIC device for data center and cloud infrastructure. Built on TSMC’s N5 process and measuring 625 mm2, this device incorporates PCIe Gen5 protocol, high-speed multi-protocol 112-Gbps SerDes, HBM2e memory operating at 3.6 Gbps, and 3.6-Tbps Die2Die PHY IP utilizing TSMC CoWoS interposer technology.
High bandwidth and high performance
5nm ASIC device offers high bandwidth Die2Die PHY for multi-die SoC and silicon disaggregation and high performance and high-density standard cell libraries and memory compilers.
Kevin Zhang, senior vice president of business development at TSMC, said,
“Broadcom’s pioneering ASIC leverages both N5, the industry’s most advanced silicon technology, and our high-performance CoWoS integration solution to address the demanding requirements of next-generation cloud and data center applications. We’re excited to see the new applications Broadcom’s ASIC platform will enable and look forward to continued partnership to empower end customers and their innovations.”
Benefits of 5nm ASIC platform vs. previous generation
- 2x increase in the on-die computation for training and inference applications
- 2x to 4x increase in memory bandwidth with HBM2e and HBM3 PHY
- 2x higher bandwidth serial links with 112-Gbps SerDes
- Up to 30% reduction in power per given work function
- System size and cost reduction with advanced packaging solutions
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