Chip and silicon IP provider, Rambus announced the general availability of Compute Express Link 2.0 and PCI Express 5.0 controllers with integrated Integrity and Data Encryption modules. The zero-latency IDE controller, developed by the newly acquired PLDA’s engineering team, delivers security and performance at full 32 GT/s speed.
Zero-latency IDE
The Build-in IDE modules in Rambus CXL 2.0 and PCIe 5.0 controllers employ a 256-bit AES-GCM symmetric-key cryptographic block cipher, helping chip designers and security architects to ensure confidentiality, integrity, and replay protection for traffic that travels over CXL and PCIe links. Some of its key features include:
- IDE security with zero latency for CXL.mem and CXL.cache
- Robust protection from physical security attacks, minimizing the safety, financial, and brand reputation risks of a security breach
- IDE modules pre-integrated in Rambus CXL 2.0 and PCIe 5.0 controllers reduce implementation risks and speed time-to-market
- Complete CXL 2.0 and PCIe 5.0 interconnect subsystems when controllers are combined with Rambus CXL 2.0 and PCIe 5.0 PHYs
Sean Fan, chief operating officer at Rambus said,
“Successful enablement of CXL use models in data-intensive applications, such as memory sharing between processors and attached AI accelerators, requires security at ultra-low latency. Delivering controllers with zero-latency security is a testament of our ability to accelerate the development of CXL solutions through the recent acquisition of PLDA, and showcases our unique position to provide integrated interface and security IP solutions.”